1. Field of the Invention
Embodiments of the invention generally relate to methods for depositing materials on substrates, and more specifically to methods for filling apertures within a high aspect ratio contact.
2. Description of the Related Art
Multilevel, 45 nm node metallization is one of the key technologies for the next generation of very large scale integration (VLSI). The multilevel interconnects that lie at the heart of this technology possess high aspect ratio features, including contacts, vias, lines, and other apertures. Reliable formation of these features is very important for the success of VLSI and the continued effort to increase quality and circuit density on individual substrates. Therefore, there is a great amount of ongoing effort being directed to the formation of void-free features having high aspect ratios of 10:1 (height:width) or greater.
Copper and tungsten are choice metals for filling VLSI features, such as a submicron high aspect ratio contact (HARC) on a substrate. Contacts are formed by depositing a conductive interconnect material, such as copper or tungsten into an aperture (e.g., via) on the surface of an insulating material disposed between two spaced-apart conductive layers. A high aspect ratio of such an opening may inhibit deposition of a conductive interconnect material to, fill an aperture. Although copper and tungsten are popular interconnect materials, deposition processes for depositing these materials may suffer by forming a void or a seam within the contact plug, as illustrated in FIG. 1C.
FIGS. 1A-1B depict a schematic cross-sectional view of an integrated circuit device on substrate 100 containing aperture 105 formed in dielectric layer 104 to expose contact layer 102. During a deposition process that may include chemical vapor deposition (CVD) or atomic layer deposition (ALD), metal layer 106 is deposited on dielectric layer 104 and within aperture 105 including on contact layer 102 and the sidewalls of dielectric layer 104 to form plug 103. Near opening 107 of plug 103, metal layer 106 may pinch off, depicted in FIG. 1C, so that plug 103 maintains a seam or void 108 therein. During a subsequent chemical mechanical polishing (CMP) process that removes a portion of metal layer 106 and dielectric layer 104 from the surface of substrate 100, void 108 may be breached or exposed to form gap 110 within plug 103, as illustrated in FIG. 1D. FIG. 1E depicts conductive layer 112 (e.g., copper) deposited on substrate 100 forming void 114 by enclosing gap 110. Substrate 100 may contain additional layers of material depending on the overall architecture of the electronic device. For example, dielectric layer 104 may be covered by a barrier layer (not shown) thereon prior to the deposition of conductive layer 112 or conductive layer 112 may also contain a barrier layer (not shown) thereon prior to the deposition of layer 120.
Defects, such as a seam or void 114, may cause a series of problems during the fabrication of electronic devices depicted herein. The resistance to current flow through plug 103 is impaired due to the lack of conductive material in void 114. However, a more serious obstacle during fabrication is the displacement of voids from one layer to the next. For example, subsequent fabrication processes of substrate 100 may include the deposition of layer 120 (e.g., dielectric layer) on conductive layer 112. During subsequent thermal processing, such as an annealing process, material 116 from conductive layer 112 may diffuse into void 114 and form void 118 within conductive layer 112. As illustrated in FIG. 1F, material 116 may not diffuse completely to the bottom of void 114. The defect formed in conductive layer 112, such as void 118, will increase the resistance of the circuit containing the defect and thus affect device performance. Ultimately, the defects in conductive layer 112 can affect the device yield of the fabricated substrate.
Therefore, a need exists for a method to fill a contact level aperture with a conductive contact material, such that the contact material is deposited free of voids, seams and other defects.